1. Field of the Invention
The present invention relates to a frequency synthesizer, and more particularly, to a frequency synthesizer with auto loop gain calibration.
2. Description of the Related Art
In current wireless transceivers, a phase locked loop circuit generates carrier signals. The phase locked loop circuit comprises a phase frequency detector, a low pass filter, a voltage control oscillator, and a frequency divider. A reference clock signal and a divided signal output from the divider are applied to the phase frequency detector for outputting an error signal. After filtering by the low pass filter, the output signal is input into the voltage control oscillator for generating a corresponding frequency which is then transmitted as feedback to the frequency divider. Thus the output carrier signal from the phase locked loop circuit occupies a determined frequency.
The output carrier signal is then modulated by a modulator to generate a modulated signal. A conventional method modulates the oscillator directly. When a wanted carrier frequency is locked by the phase locked loop circuit. A feedback path in the phase locked loop circuit is cut off, and the oscillator is modulated directly. The problem here is that the feedback path must be linked back periodically to prevent over frequency shift. The oscillator must additionally be isolated from surrounding noise to prevent interruptions.
In U.S. Pat. No. 4,965,531; Relay ,et al. describes a modulating method. In U.S. Pat. No. 4,864,257; Vandergraaf ,et al describes another modulating method. Though the carrier frequency of the mentioned two patents do not cause frequency shifts due to the close loop of the synthesizers, the bandwidth, however is limited. Due to filtering of the high frequency, a distorted frequency is filtered so a frequency is generated, resulting in limited signal.
In U.S. Pat. No. 4,864,257; Vandergraaf ,et al. describes a circuit to compensate for the limited frequency band. The circuit applies an inverse frequency to compensate for the limited frequency of the phase locked loop circuit. Process and the temperature issues, however, affect the mismatch between the compensated frequency and the limited frequency. Therefore, in U.S. Pat. No. 6,008,703; a digital pre-emphasis filter is employed to lessen the effects of process and temperature. If the channel and the bandwidth increase, however, the number of oscillators and the operational range also increase. Thus, frequency mismatching situation still occurs. In U.S. Pat. No. 6,515,553; Norman ,et al. describes a dual-port modulation, employing a high-pass filter for passing the high frequency portion of a signal and adding the high frequency portion of the signal to a control circuit of an oscillator of a phase locked loop circuit. Thus a full-pass filter can be achieved. Process and the temperature issues still exist, however, and the circuit area of the analog circuit is greater than a digital circuit. Thus increasing costs, integrality and reducing efficiency.
FIG. 1 shows a conventional frequency synthesizer comprising a pre-emphasis filter 15. The phase locked loop circuit 1 comprises a phase detector 10, a low pass filter 11, a voltage control oscillator 12, an N/N+1 frequency divider 13 and a Σ−Δ modulator 14. The phase locked loop circuit 1 comprises low pass filter 11 for filtering the high frequency portion of the transmitted signal. A pre-emphasis filter 15 is installed for overcoming the low pass filter which filters the high frequency portion of the transmitted signal. The frequency response of the pre-emphasis filter 15 is the inverse of the closed loop frequency response of the synthesizer as shown in FIG. 2A. A flat frequency response is generated by the two frequency responses.
A synthesizer, however, operates on a wild frequency band, and different frequency bands of various voltage control oscillators are installed in a synthesizer. Due to the limited size of a circuit area, however, only one pre-emphasis filter is employed, and gain mismatch occurs. Thus the frequency response is different, resulting in signal distortion. As shown in FIG. 2B and FIG. 2C, in FIG. 2B, bandwidth of the pre-emphasis filter 15 is narrower than the phase locked loop circuit 1 (fc−pre<fc−p11). In FIG. 2C, bandwidth of pre-filter 15 is wilder than the phase locked loop circuit 1 (fc−pre>fc−p11). The frequency mismatch occurs according to the pre-emphasis filter 15 and the phase locked looped circuit 1, resulting in transmitted signal distortion (fc−pre<fc−p11).